Field of the Invention
Embodiments of the present invention relate generally to power gating and, more specifically, to selective power gating to extend the lifetime of sleep FETs.
Description of the Related Art
A conventional computer system is typically configured to implement power gating in order to gate off processing elements when those elements are not in use. Power gating reduces power consumption by preventing leakage that would otherwise draw unnecessary power. A common technique for implementing power gating is to couple a series of sleep field-effect transistors (FETs) between a power source and a logic block that consumes power, or to couple a series of sleep FETs between the logic block and ground. The former arrangement of FETs is known in the art as a “header,” while the latter is known as a “footer.” A header or footer may be referred to generally herein as a “power-gating array.”
When the logic block is operational and consumes power, the sleep FETs within a power-gating array are activated and the logic block can then draw power. When the logic block is not operational and does not consume power, the sleep FETs are deactivated and the logic block cannot draw power, thereby preventing leakage. Since each sleep FET induces a voltage drop between the power source and the logic block (or between the logic block and ground, as the case may be), a power-gating array typically includes many sleep FETs arranged in parallel with one another. With this configuration, the resistance of the array as a whole can be minimized.
Modern computer systems may also be configured to implement dynamic voltage and frequency scaling (DVFS). DVFS is a technique whereby the voltage supplied to a logic block, and the clock frequency of that logic block, can be scaled up or down depending on available power or depending on the power needs of the logic block. When DVFS and power gating are implemented in conjunction with one another, the number of sleep FETs within a power-gating array coupled to the logic block must be carefully chosen to ensure that the voltage drop across the array is small enough to support the maximum operating voltage of the logic block.
However, one problem with this approach is that the sleep FETs within the power-gating array may deteriorate over time due to various physical factors, including bias temperature invariance (BTI) and time-dependent dielectric breakdown (TDDB). Increased activation of sleep FETs typically exacerbates these factors. With power-gating switches that include many parallel sleep FETs, the likelihood that a given FET will deteriorate and fail is increased. If any sleep FETs within the power-gating array deteriorates in performance or ceases to function, the voltage drop across that array may increase, and the array may not be able to support the maximum operating voltage of a logic block coupled thereto.
Accordingly, what is needed in the art is an effective technique for reducing the deterioration of sleep FETs in power-gating arrays.